The present invention relates to a semiconductor integrated circuit, and more specifically to a delay circuit thereof.
In conventional semiconductor integrated circuits, a delay circuit is interposed between two circuit systems so as to adjust timings, for instance. The delay circuit as described above is usually composed of logic gates for generating pulse signals or timings between two signals and activated on the basis of a single supply voltage.
In the conventional delay circuit, however, in case the supply voltage fluctuates, since the charge and/or discharge time of parasitic capacitances of the logic gates fluctuates, there exists a problem in that the delay time also fluctuates, as shown in FIG. 1. In the case of a SRAM (static RAM), for instance, a delay circuit is used to apply an equalize pulse after the potential level of a word line has risen. In this case, if the supply voltage becomes high, since the charge and/or discharge is completed at high speed in the respective logic gates, the potential level of the equalize pulse of the SRAM falls earlier than a predetermined timing, with the result that the equalize pulse falls in level before the potential level status of the word line is not yet changed, thus causing an erroneous operation.